PCB hole concept
- Release on:2019-02-22
Basic street concept
Via is one of the important components of a multilayer PCB. The cost of drilling is usually between 30% and 40% of the cost of the PCB. Simply put, every hole in the PCB can be called away. In terms of function, the vias can be divided into two types: one is used as an electrical connection between the layers; the other is used to fix or position the device. In terms of process, these routes are generally divided into three categories, namely blind streets, underground streets and streets. Blind streets are located on the top and bottom surfaces of the printed wiring board and have a depth for connecting the surface wiring to the underlying internal wiring. The depth of the holes usually does not exceed a certain ratio (opening).
The buried hole refers to a connection hole located in the inner layer of the printed wiring panel, which does not extend to the surface of the printed circuit. The above mentioned two types of holes are located in the inner layer of the printed circuit and are completed by a process of forming the through hole before rolling and several inner layers can be overlapped during the formation of the through holes. The third type is called a through hole and the hole passes through the entire circuit board and can be used to implement the internal interconnection or as a mounting hole for the component. Since the routes are easier to implement in the process and cost less, most printed circuit boards use it without the need for two more routes. The through holes described below are considered through holes unless otherwise specified.
From the point of view of design, a path consists mainly of two parts, one is a hole in the middle and the other is an area around the hole. The size of these two parts determines the size of the streets. Obviously, in the design of high-speed and high-density PCBs, the designer always hopes that the smaller the way, the better, so that more space on the wiring can be left on the board. Furthermore, the path, the parasitic capacity, is less. Smaller, more suitable for high-speed circuits. However, reducing the size of the hole also entails an increase in costs, and the size of the hole in the street can not be reduced indefinitely. It is limited by process techniques such as drilling and plating: the smaller the hole, the smaller the drill The longer the hole, the easier it is to deviate from the central position; and when the depth of the hole exceeds 6 times the diameter of the hole, there is no guarantee that the wall of the hole can be plated uniformly with the copper. For example, if a normal 6-layer PCB has a thickness (through-hole depth) of 50Mil.
Thus, under normal conditions, PCB manufacturers can provide a minimum diameter of 8Mil. With the development of laser drilling technology, hole sizes can be even smaller and smaller. Generally, the passage hole with a diameter of 6Miles or less is called a micro hole. Micropores are often used in HDI (High Density Interconnect Structure) designs, which allow vias to be placed directly on the pads (Via-in-pad), greatly improving circuit performance and saving space in the cabling.
The vias appear as discontinuous breakpoints on the transmission line, causing reflections in the signal. Generally, the equivalent impedance of one route is about 12% lower than that of a transmission line. For example, a 50-ohm transmission line is reduced by 6 ohms when it passes through a street (in particular, the street size is also related to the street's thickness, not an absolute decrease). However, the reflection of the through hole due to the impedance discontinuity is actually very small and its reflection coefficient is only: (44-50) / (44 + 50) = 0.06. The problem of the via hole is more concentrated on parasitic capacitance and inductance. Impact.
Via parasitic capacitance and inductance
The same hole in the street has a parasitic parasitic capacity. If the diameter of the through hole of the through hole on the base layer is known to be D2, the diameter of the pad away is D1, the thickness of the PCB is T and the dielectric constant of the substrate of the board. For ε, the parasitic viability is similar to:C = 1.41εTD1 / (D2-D1)
The main effect of the parasitic capacitance of the pathway on the circuit is to extend the signal rise time and reduce the circuit speed. For example, for a PCB with a thickness of 50Mil, if the diameter of the pad away is 20Mil (the diameter of the hole is 10Mils) and the diameter of the welding mask is 40Mil, we can approximate the hole using the formula above. The parasitic capacity is approximately:
C = 1.41x4.4x0.050x0.020 / (0.040-0.020) = 0.31pF
The amount of rise time caused by this part of the capacity is approximately:
T10-90 = 2.2C (Z0 / 2) = 2.2x0.31x (50/2) = 17.05ps
From these values it can be seen that, although the effect of the increase and of the delay caused by the parasitic capacity of a single path is not obvious, if the path is used several times in the track for the passage between the two layers, multiple. , design must be carefully considered. In the current design, the parasitic capacitance can be reduced by increasing the distance between the copper pad and the way (Anti-pad) or by reducing the diameter of the pad.
Parasitic inductance exists in the street hole and there is parasitic inductance. In the design of high-speed digital circuits, the parasitic inductance of the through-hole is often more damaging than the parasitic capacitance. Its parasitic series inductance weakens the contribution of the bypass capacitor and reduces the filtering efficiency of the entire feeding system. We can simply calculate the parasitic inductance of an approximation route using the following empirical formula:
L = 5.08h [ln (4h / d) +1]
Where L is the inductance of the way, h is the length of the way, and d is the diameter of the central hole. From the equation it can be seen that the diameter of the way has less influence on inductance and the greater influence on inductance is the length of the way. Still using the previous example, the street inductance can be calculated as:
L = 5.08x0.050 [ln (4x0.050 / 0.010) +1] = 1.015nH
If the signal rise time is 1 ns, the equivalent impedance is: XL = πL / T10 - 90 = 3.19 Ω. This impedance can not be ignored in the presence of high-frequency current. It is important to note that the bypass capacitor must pass through two vias when connecting the supply layer and the ground plane, so that the pathway parasitic inductance is multiplied.
How to use vias
Through the above analysis of the vias parasitic characteristics, we can see that in the design of high-speed PCBs, seemingly simple vias often have a big negative effect on the design of the circuit. In order to reduce the adverse effects of vias parasitic effects, it is possible to do as much as possible in the design:
A Consider the size of the streets of reasonable size in terms of cost and signal quality. If necessary, consider using different sizes of vias. For example, for power or ground routes, consider using larger dimensions to reduce impedance, while for signal traces, use smaller paths. Obviously, as the street size decreases, the corresponding cost increases.
B The two formulas discussed above can be concluded that the use of a thinner PCB will help reduce the two parasitic parameters of the route.
The signal traces on the PCB C should not be changed as much as possible, ie, try not to use unnecessary vias.
D The power and grounding pins must be made near the hole and the cable between way and pin should be as short as possible. More paths can be considered in parallel to reduce the equivalent inductance.
E Place some grounding paths near the signal change level paths to provide the most recent signal loop. It is even possible to place some extra-earth ways on the PCB.
F For high density, high density PCB boards, consider using micro vias.
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