Testing & Inspection
The full verification chain in table form — inspection gates, electrical testing, imaging and X-ray, destructive reliability checks and the documents that ship with your batch. Every line is a capability you can audit. Why it matters: on a 24-layer board a defect found at final test has already absorbed the cost of every upstream step — these gates catch it while it is still cheap to fix. Traceability: every result is logged per panel and included in the shipping report — electrical yield and impedance CPK become evidence your customer can audit. Tell us the class on your drawing and we inspect, judge and report to it. Any anomaly flagged by AOI, X-ray or AXI can be cross-sectioned and documented. Sample-based by design: these tests consume the boards they measure — they run on samples and coupons, and the results ship as documented evidence with the batch. CPK reported per batch · judged against your drawing tolerance · issued as a PDF with each shipment. Ask for a real sample report set from a comparable build — we will send the document, not a brochure page. Reports are issued for every production batch — sample sets are available before you place the order. Five tables, one evidence chain: gates catch defects while they are still cheap to fix, electrical test proves what imaging cannot, X-ray and cross-sections reveal what is buried inside the stack, and every batch ships with its own measured data — the boards you receive stay untouched.Every Layer. Every Net. Verified.
Full-Process Quality Gates
Incoming material → Final QC · 8 gatesGate What Is Checked What It Prevents 01Incoming Material Inspection Laminate, copper foil & prepreg quality before release to production Hidden material defects entering the stack-up 02Inner-Layer AOI Etched inner patterns — opens, shorts, line width & pinholes Defects being buried inside the multilayer build 03X-Ray Layer Registration Post-lamination layer alignment — targeting ±25 µm Misregistered buried vias & interlayer shorts 04Hole Quality Inspection Drilled position & wall condition — mechanical & laser vias Plating faults, barrel cracks and via-related opens 05Outer-Layer AOI Final etched pattern before solder mask — full-coverage scan Net-level defects reaching the finished board 06Solder Mask & Finish Inspection Mask coverage, surface finish thickness & appearance Soldering issues, corrosion and finish-related failures 07Profile & Routing Inspection Final outline, edge quality & dimensional tolerances Fit and assembly problems at the customer side 08Final QC (FQC) 100% visual inspection per IPC-A-600 before packing Any cosmetic or latent defect from ever shipping Electrical Verification
Continuity · Isolation · Impedance100% 4-Wire ±10 / 5% CPK Net Coverage Kelvin Sensing Impedance Targets Data Delivered Flying probe checks opens & shorts on every net of every board Contact-resistance-free readings on fine-pitch, high-reliability nets TDR on controlled nets & coupons, with CPK data reported Electrical test results ship with every batch for your audit Test Method Detects Precision / Target Best For Flying Probe Test · 100% full coverage Opens, shorts & isolation faults, verified net-by-net against the netlist Continuity / isolation checked to the specified threshold on 100% of nets Prototypes, high-layer boards and medium runs without fixture cost Four-Wire Kelvin Test Marginal low-resistance faults on fine-pitch & high-reliability networks True four-wire measurement — no contact-resistance error Dense BGA breakouts, power nets and customer-specified critical nets ICT — Fixture Test Opens & shorts across the full netlist via a dedicated test fixture Fixture-based — highly repeatable test at production speed Volume batches and repeat orders with a stable design TDR Impedance Test Characteristic-impedance deviation on high-speed & differential nets Targets ±10% (standard) / ±5% (controlled), measured on-net or coupon Controlled-impedance, high-speed and RF stack-up designs Vision & X-Ray Inspection
AOI · X-Ray · AXI · IPC-A-600Method What It Sees What It Verifies Best For AOI — Inner & Outer Layers Opens, shorts, line width and pinholes on every copper layer Each layer individually — inner first, outer before solder mask HDI, fine-line and high-density multi-layer designs X-Ray Layer Registration Layer-to-layer alignment and buried / blind via positions inside the stack Registration against design, measured through the laminated board High-layer-count stacks where small shifts compound layer by layer X-Ray Back-Drill Verification Back-drill depth, remaining stub and buried / blind via condition Stub length against your stack-up spec, before finish is applied High-speed and controlled-impedance designs with back-drilled vias AXI & Final Visual (FQC) Hidden hole and back-drill features by AXI, plus every visible surface by eye Final acceptance to the IPC-A-600 class called out for your part The last gate before packing — nothing ships without passing both IPC-A-600 Class Product Type Acceptance Level Class 1 General Electronic Products The most basic acceptance level — for boards where the main requirement is that the assembly functions Class 2 Dedicated Service Products Higher cosmetic and workmanship expectations for products with a defined service life and reliability demand Class 3 High Reliability Products The strictest acceptance level — for applications where continuity of service is critical Reliability Verification
Destructive · sample-based · 6 testsTest What It Reveals Criteria Report Microsection A coupon or sample is potted, ground and polished, then measured under magnification Hole copper thickness, layer alignment and back-drill stub assessed against the class on your drawing (IPC-6012) Cross-section images with measurement call-outs per hole Thermal Stress — 288 °C Boards are floated on molten solder or hot oil at 288 °C — the standard stress that exposes weak plating No delamination, blistering or barrel cracks after stress (IPC-TM-650 method) Pre / post images plus microsection of stressed holes Thermal Shock Cycling Repeated hot-to-cold cycling drives expansion stress through vias and laminate interfaces No delamination, cracking or resistance drift after the cycles you specify Cycle log with temperatures, plus post-cycle microsection Ionic Contamination (ROSE) Residual flux and handling salts left on the surface after processing Ionic residue below the limit agreed for your application (ROSE method) Measured value in µg NaCl equivalent per cm² Solderability The finish is dipped or tested on a wetting balance to prove the surface takes solder cleanly Complete wetting with no dewetting or non-wetting areas (J-STD-003) Wetting curve and dipped-sample photographs Warp & Twist Bow and twist are measured, not eyeballed — the board must not fight your placement window Bow and twist within the assembly limit you specify (IPC-TM-650 method) Measured values per panel with method reference Data & Report Delivery
Impedance · Microsection · Yield · AQLDocument What It Contains Issued Impedance Test Report Measured impedance vs target for controlled nets and coupons, with the CPK of the batch With every batch Microsection Report Cross-section images with measured hole copper, layer alignment and back-drill stub length Sample-based Electrical Yield Summary Opening and short counts with pass / fail statistics for the whole batch, per netlist With every batch AQL Outgoing Certificate Outgoing inspection to the agreed AQL level, issued as a certificate With every shipment Net Target Measured Result L3 · USB_DP 45.0 Ω ±10% 44.4 Ω PASS L4 · CLK_100M 50.0 Ω ±10% 50.6 Ω PASS L7 · DIFF_PAIR_0 90.0 Ω ±5% 91.8 Ω PASS What You Can Audit Detail Impedance Measured value vs target for each controlled net, with CPK Hole integrity Copper thickness and stub length, visible in cross-sections Electrical yield Opens and shorts statistics for the whole batch Outgoing quality AQL inspection result and certificate
