TECHNICAL GUIDES
POFV Process Complete Guide: Plated Over Filled Via (VIPPO) Technology
PCB ADVANCED PROCESS · TECHNICAL GUIDE
POFV Process Complete Guide
Plated Over Filled Via · Via-in-Pad Plated Over (VIPPO) Technology
01
What is POFV? Definition · Terminology · Core Concept
▎Full Name & Definition
POFV stands for Plated Over Filled Via — an advanced PCB manufacturing process in which a via hole is first completely filled with resin or conductive material, cured and planarized, then copper-plated over the surface to form a flat, solderable "copper cap" structure.
▎Industry Driver
As BGA pitch shrinks from 0.65mm → 0.5mm → 0.4mm → 0.3mm, chip I/O counts exceed 1,000+. Traditional dog-bone fanout routing no longer fits. POFV enables vias directly under component pads (Via-in-Pad), making it the industrial standard for HDI high-density designs.
▎The Core Problem: Solder Wicking
When unfilled vias sit under component pads, molten solder flows down into the via barrel via capillary action during reflow soldering → causing solder voids, cold joints, pad lifting, and BGA ball dropout. POFV completely fills the via and plates copper over it, eliminating this risk and boosting BGA first-pass yield from 83% to 99.2%, with MTBF extended to over 120,000 hours.
02
Standard Via vs. POFV Structure · Performance · Application
✕ Standard Hollow Via
- Solder wicks down via barrel by capillary action
- Solder void rate can reach 25–30%
- High risk of pad lifting and cold joints
- Cannot be used for Via-in-Pad designs
- Long signal path; poor high-frequency performance
VS
✓ POFV Copper-Cap Structure
- Resin fully fills via — zero trapped voids
- Copper cap creates a perfectly flat surface
- BGA first-pass yield ≥ 99.2%
- Supports direct Via-in-Pad component placement
- Ultra-short signal path; superior high-speed performance
03
Manufacturing Process Flow Step-by-Step Breakdown
Scheme A: Two-Drill Process Classic · Most Reliable · Widely Used
STEP 01
Laser / Mechanical Drilling
Via diameter φ0.075–0.30mm
Tolerance ±0.025mm
Tolerance ±0.025mm
STEP 02
Via Metallization
Electroless Cu deposition
Electrolytic plating ≥15μm
Electrolytic plating ≥15μm
STEP 03
Vacuum Resin Plugging
Vacuum ≤ −95kPa
Pressure 0.3–0.5MPa
Fill efficiency >75%
Pressure 0.3–0.5MPa
Fill efficiency >75%
★ Critical
STEP 04
Staged Cure Baking
130°C × 30 min
→ 150°C × 60 min
Uniform cure, low stress
→ 150°C × 60 min
Uniform cure, low stress
★ Critical
STEP 05
Grinding / Planarization
Remove excess resin
Surface Ra ≤ 0.5μm
Surface Ra ≤ 0.5μm
↓
↓
↓
↓
↓
STEP 06
Cu Reduction / Desmear
Reduce surface Cu to 5–8μm
Clean residual resin
Clean residual resin
STEP 07
2nd Drilling Pass
Drill component &
tooling holes
tooling holes
STEP 08
Copper Cap Plating
2nd electroless Cu + panel plate
Cap Cu over resin surface
Inner layer ≥16μm
Cap Cu over resin surface
Inner layer ≥16μm
★ Critical
STEP 09
Pattern Transfer & Etch
Dry film exposure
& circuit etching
& circuit etching
STEP 10
Solder Mask & Surface Finish
ENIG / HASL / OSP
Final inspection & shipment
Final inspection & shipment
Done
Scheme B: Single-Drill Process Higher Throughput · Suitable for Mass Production
STEP 01
Drill All Holes at Once
VIP holes + component holes
+ tooling holes together
+ tooling holes together
STEP 02
Via Metallization
Electroless Cu + plating
Wall Cu ≥15μm
Wall Cu ≥15μm
STEP 03
Selective Resin Plugging
Aluminum sheet / dry film
masks non-VIP holes
Fills only VIP positions
masks non-VIP holes
Fills only VIP positions
★ Critical
STEP 04
Cure → Grind → Cu Reduction
Staged baking
Surface planarization
Surface planarization
STEP 05 →
Cu Cap → Normal Flow
Electroless Cu + panel plate
→ Standard subsequent steps
→ Standard subsequent steps
Done
04
Via Cross-Section Structure Layer Stack · Dimensional Requirements
▎POFV Via Layer Stack
Soldering face
5 – 25 μm
Cu foil layer
🟩 Resin Fill (Epoxy / Conductive)
← Cu wall ≥15μm ｜ Resin Fill ｜ Cu wall →
Board thickness
Inner connection
▶ Design Requirements
• Connect Cu cap to inner-layer ground/power plane for thermal relief
• Pad-to-via ratio ≥ 1.8:1 to ensure sufficient annular ring
• Surface dimple depth < 1 mil to ensure solderability
• Pad-to-via ratio ≥ 1.8:1 to ensure sufficient annular ring
• Surface dimple depth < 1 mil to ensure solderability
▎Cure Profile: Direct vs. Staged Bake
✗ Wrong: Single-Step High-Temp Cure
✓ Correct: Staged Ramp Cure
▶ Copper Cap Plating Line Controls
• Keep plating line running continuously — insert 5 dummy boards every 30 VIP panels
• Maximum 120 boards per run; then interleave with standard through-hole panels
• Complete panel plating within 4 hours of electroless Cu deposition
• Pre-treatment acid bath Cu ions ≤ 100 ppm
• Maximum 120 boards per run; then interleave with standard through-hole panels
• Complete panel plating within 4 hours of electroless Cu deposition
• Pre-treatment acid bath Cu ions ≤ 100 ppm
05
Key Process Parameters Quality Control Metrics
Plugging Vacuum Level
≤ −95
kPa · Ensures zero trapped bubbles
Pressure gradient: 0.3–0.5 MPa
Pressure gradient: 0.3–0.5 MPa
Cu Cap Thickness (Inner Layer)
≥ 16μm
Prevents laser via punch-through
Outer-layer final: 5–12μm
Outer-layer final: 5–12μm
Staged Cure Temperature
130→150
°C · Uniform cure profile
Duration: 30 min + 60 min
Duration: 30 min + 60 min
Surface Planarity Ra
≤ 0.5μm
Post-CMP polishing target
Rough polish ±2μm → Fine ±0.5μm
Rough polish ±2μm → Fine ±0.5μm
Via Fill Efficiency
> 75%
Minimizes void risk
Resin deaeration ≥30 min
Resin deaeration ≥30 min
BGA First-Pass Yield
99.2%
+16.2% vs. unfilled vias
MTBF extended to 120,000 hrs
MTBF extended to 120,000 hrs
| Application Scenario | Cu Cap Thickness Requirement | Visualization | Key Note |
|---|---|---|---|
| Inner-layer cap (laser blind via above) | ≥ 16μm | Prevents laser punch-through — highest requirement | |
| Outer layer, negative-tone process (semi-finished) | 12 – 18μm | Includes allowance for subsequent grinding & micro-etch | |
| Outer layer, positive-tone process (after 1st plate) | 5 – 8μm | Additional pattern plating will add thickness later | |
| Outer-layer final finished product | 5 – 12μm | Meets customer spec after surface finish application |
06
IPC-4761 Via Fill Classification POFV = Type VII — Highest Grade
I
Solder Mask
Plug
Plug
No Cu cap
II
Conductive
Ink Fill
Ink Fill
No Cu cap
III
Partial
Resin Fill
Resin Fill
No Cu cap
IV
Full
Resin Fill
Resin Fill
No Cu cap
V
Resin Fill
+ Cap Film
+ Cap Film
Partial cap
VI
Conductive
Material Fill
Material Fill
No Cu cap
VII
Full Fill
+ Cu Cap ⭐
+ Cu Cap ⭐
POFV Standard
07
Six Key Application Domains Industry Needs · Technology Match
Smartphones & Wearables
BGA pitch ≤ 0.4mm, I/O count >1,000. Extreme board area constraints demand POFV for HDI multi-layer fanout routing. Flagship SoCs (Qualcomm, MediaTek, Apple) all rely on this technology.
BGA pitch ≤0.4mm5G Communications
mmWave (28/39GHz) demands ultra-short signal paths. POFV eliminates stub effects, reduces return loss and crosstalk — a core process choice for 5G base stations, routers, and switches.
High-Freq / mmWaveAI Servers & Accelerator Cards
GPU/NPU packages with 5,000+ I/Os. Low-impedance PDN requires POFV connecting inner-layer copper pours. Proven: BGA yield 83% → 99.2%; MTBF >120,000 hours.
AI Compute / HDPAutomotive Electronics (ADAS)
Operating range −40°C to 125°C with severe vibration. POFV resin fill provides mechanical support. Passes IPC-6016 Class 3: 1,000 thermal-shock cycles with zero delamination.
AEC-Q200 / Class 3Medical Electronics
Implantable devices (pacemakers, neuromodulators) require near-zero failure tolerance. POFV fill improves hermeticity, prevents fluid ingress, and enables more function in minimal volume.
High-Reliability / ImplantAerospace & Defense
Avionics-grade PCBs must survive extreme environments (hard vacuum, radiation). Aerospace-grade resins have zero outgassing. POFV structures pass MIL-spec vibration and shock testing at reduced weight.
MIL-PRF / Space Grade08
Typical Failure Modes & Prevention Quality Control
Cratering (Volcano Effect)
Residual air bubbles in resin expand at reflow temperature, erupting through the copper cap surface
▶ Maintain vacuum ≤ −95kPa; deaerate resin thoroughly (mix ≥30min)
Copper Cap Crack
Insufficient cap thickness (<5μm) or uncontrolled rework cycles grinding cap below minimum
▶ Enforce per-scenario Cu thickness specs; limit rework; inspect first-article before each rework
Pad Lifting / Land Separation
CTE mismatch between resin and copper foil; cumulative thermal-cycle stress exceeds adhesion limit
▶ Select CTE-matched resin; connect POFV via to inner-layer solid copper plane for stress relief
Cold Tear (BGA Corner Crack)
BGA corner warpage + unidirectional solidification causes solder joint to "cold-tear" during cooling
▶ Connect POFV vias at BGA corners to inner-layer ground/power planes for uniform heat extraction
Electroless Cu Void on Cap
Bath activity drops after line stoppage; discontinuous electroless Cu layer cannot support subsequent plating
▶ Continuous production + dummy board insertions; complete panel plating within 4 hrs of electroless Cu
Interface Delamination
Moisture ingress at resin/copper interface; steam pressure during reflow separates the bond
▶ Pre-bake panels at 120°C to remove moisture; use SAT (acoustic scan) for incoming inspection
09
Via Technology Comparison IPC-4761 Seven Fill Types
| Via Technology | Fill Material | Cu Overplate | Surface Planarity | Reliability | Cost Premium | Via-in-Pad |
|---|---|---|---|---|---|---|
| Standard Through-Via (unfilled) | None | No | Poor | Moderate | Lowest | Not supported |
| Resin-Plugged Via (Type IV) | Epoxy resin | No | Moderate | Good | Low | Not recommended |
| Conductive Filled Via (Type VI) | Cu paste | No | Moderate | Good | Medium | Limited |
| ⭐ POFV (Type VII) | Resin / Cu paste | ✓ Yes | Excellent | Very High | +20–40% | Full support |
| Blind Via + POFV Stack | Resin | ✓ Yes | Excellent | Very High | Highest | Full support |
10
Design for Manufacture (DFM) Rules Key Constraints for PCB Engineers
📐 Geometric Design Constraints
Via diameter (recommended range)0.10 – 0.30mm
Maximum processable via diameter≤ 0.30mm (>12mil = difficult)
Pad-to-via diameter ratio≥ 1.8 : 1
Adjacent VIP center-to-center spacing≥ 300μm
Minimum Cu cap thickness≥ 1 mil (25μm)
Max allowable surface dimple< 1 mil (25μm)
Blind via aspect ratio (AR)< 1 : 1
🏗️ Stacked Via Design Recommendation
✗ Stacked (Co-axial) — Not Recommended
✓ Offset (Staggered) — Recommended
For multi-layer VIP stacks (e.g. 6+4+6 HDI build-up), offset vias by ≥50μm in X/Y to prevent cumulative resin shrinkage stress causing interlayer displacement.
▶ EDA Tool Support
Cadence Allegro and Mentor Xpedition include integrated POFV DFM check modules. They automatically generate Gerber 274X-compatible Via Fill Map files to drive exposure and plating equipment.
11
Future Technology Trends Next-Generation Innovations
Ultra-Micro POFV (φ0.05mm)
Leveraging nano-silica-modified epoxy resin (particle size <50nm) for complete fill of sub-50μm vias, enabling Chiplet heterogeneous integration and breaking conventional fill capability limits.
Enables Chiplet IntegrationCo-W Alloy Barrier Layer
Introducing a cobalt-tungsten (Co-W) alloy barrier layer (only 0.2μm thick) to suppress copper atom diffusion under thermal stress. Thermal cycle lifetime extended by 3× vs. standard POFV.
3× Lifetime Improvement"Resin-Free POFV" Technology
Using copper's natural ductility — depositing graded copper thickness (20μm at bottom, 5μm at top) then low-temperature hot pressing (180°C / 30min) for densification. Validated in 3D TSV interposers: thermal conductivity +40% over conventional POFV.
+40% Thermal Conductivity1users like this.
